For a variety of reasons, an important application of III-V semiconductor devices is in field effect transistors. A common configuration is the MESFET which has a metallic electrode formed on a doped active layer which serves as a channel for the semiconductor device. Turn-on voltage limitations in that type of device tends to limit the maximum amplitude of signals which can be applied.
A number of devices have been proposed to accommodate larger amplitude signals. Among them is the MIS-like FET which interposes an insulator layer between the metallic gate and the doped active layer. The device is called MIS-like because the insulators which have been used are not true insulators, but are doped or undoped semiconductor material.
FIG. 3 illustrates, in cross-section, a typical construction for a MIS-like FET. The FET of FIG. 3 is constructed of III-V compound semiconductors including a semi-insulating GaAs substrate 1 on which an n-type GaAs layer 2 is epitaxially grown. The conventional FET of FIG. 3 generally employs a portion of layer 2 as the active layer of the FET, that is, as the channel through which the charge carriers of interest flow. An undoped layer 3, preferably of AlGaAs, is disposed on layer 2. The AlGaAs layer is epitaxially grown by a conventional technique. A gate 4 disposed on layer 3 is a conventional refractory metal gate electrode, such as WSi. Gate 4 is disposed between spaced apart n.sup.+ -type source and drain regions 5a and 5b. The source and drain regions extend from the exposed surface of layer 3 through layers 3 and 2 and into substrate 1. The source and drain regions are usually produced by ion implantation. Electrical contacts are made to the source and drain regions through source and drain electrodes 6 and 7, respectively, which may be conventional contacts, such as an alloy containing gold and germanium. Electrodes 6 and 7 may be deposited in the desired locations by employing a vapor deposition step with a conventional lift-off step.
Source and drain regions 5a and 5b are spaced apart on opposite sides of gate 4 with which they are aligned. This alignment is conventionally achieved by first depositing gate 4 and employing it as a mask during the ion implantation step that produces the source and drain regions. Gate 4 may be deposited by sputtering a WSi layer onto the exposed surface of layer 3 and removing the unwanted portions of the metallic layer by etching, such as reactive ion etching. Isolation regions 8 are disposed in layers 2 and 3 on opposite sides of the device for electrical isolation of the source and drain regions from other active regions in layers 2 and 3. Isolation regions 8 may be produced by a number of conventional techniques, including ion implantation.
In the FET of FIG. 3, the majority charge carriers, here electrons, flow through a channel in layer 2 that is disposed between the source and drain. The current flow through the channel may be constricted by the application of a sufficiently negative voltage to gate 4. That voltage produces an electric field that penetrates layer 3 to influence current in layer 2. Because of the presence of insulating layer 3, relatively large amplitude signals can be applied to gate 4 to obtain a relatively large signal response from the FET. Since source and drain regions 5a and 5b are preferably self-aligned through the use of gate 4 as a mask during ion implantation, the separation between gate 4 and source (drain) region 5a (5b) can be relatively small. The small spacing means that the source (drain) series resistance is relatively low so that a high gain FET is produced.
As is well understood in the art, in an FET of the type shown in FIG. 3, the channel between the source and drain regions behaves as a resistor when relatively low voltages are applied between the source and drain. For a particular gate-to-source voltage, once the drain-to-source voltage exceeds a threshold, the drain-to-source current remains relatively constant as the drain-to-source voltage changes. This threshold gate-to-source voltage is also referred to as the knee of the current-voltage characteristic of the FET. The desired FET operating points lie above the threshold gate-to-source voltage. The threshold voltage generally corresponds to the minimum voltage required to deplete the channel of electrons.
For the structure shown in FIG. 3, that threshold voltage is given by EQU V.sub.th =.phi..sub.B -.DELTA.E.sub.C -qN.sub.d t.sub.n (2t.sub.o +t.sub.n)/2.epsilon..
In the threshold voltage equation, .phi.B is the Schottky barrier potential between metallic gate 4 and layer 3. Generally, that potential is about 0.6 to 0.8 volts. Since layers 2 and 3 form a heterojunction and the carriers of interest are electrons, the second term of the equation, .DELTA.E.sub.C, is the discontinuity in the conduction bands of the materials in layers 2 and 3, when the FET is in thermal equilibrium. In the final term of the equation, q is the electronic charge, N.sub.d is the density of majority carriers (here, electrons) in layer 2, .epsilon. is the absolute dielectric constant of the semiconductor material, t.sub.n is the thickness of layer 2, and t.sub.o is the thickness of layer 3. In formulating the equation, it has been assumed that layer 3 is substantially intrinsic and that the densities of electrons and of holes in layer 3 are essentially the same. As a result, that layer acts much like an electrical insulator and does not significantly attenuate the electric field that originates at gate 4.
It follows from the equation that, for a given conductivity, i.e., majority carrier density level, in layer 2, there is very little selectivity in choosing the threshold voltage. In that case, only the thicknesses of layers 2 and 3 can affect the threshold voltage. Adjustment of the thickness of layer 2 can significantly alter the gain of the device as well as change the resistance of the channel extending between the drain and source regions. While that can be altered from wafer to wafer, there is no ready mechanism for producing FETs on the same wafer with different threshold voltages. That limitation presents a significant disadvantage in producing ICs.
A further disadvantage of the structure of FIG. 3 lies in the inability to equalize the densities of majority and minority carriers in AlGaAs, which is the preferred material for layer 3. The inability to equalize those carrier densities precisely means that layer 3 is not a strong insulator, i.e., that the maximum resistance of layer 3 is limited. As a result, nominally intrinsic layer 3 is actually n-type, so that a leakage current flows between gate 4 and one or both of the source and drain regions. That leakage current interferes with device performance.
In order to isolate the device of FIG. 3 from other devices in the same substrate, it is necessary that isolation regions 8 extend through both layers 2 and 3 into semi-insulating substrate 1. Isolation regions 8 may be formed by chemical etching, with or without the filling of the grooves so formed, or may be prepared by ion implantation with p-type impurities, such as magnesium, or impurities forming deep levels, such as boron. The depth of etching and ion implantation required to form isolation regions 8, i.e., penetrating both layer 2 and 3, causes problems and increases costs in manufacturing IC's with the FET of FIG. 3.